1. Field of the Invention
The present invention relates to a thin film transistor ("TFT"), and more particularly to an improved thin film transistor and a fabrication method thereof for increasing an on/off current ratio of the TFT.
2. Description of the Conventional Art
FIG. 1 shows a cross-sectional view of a conventional top gate type polycrystalline-silicon TFT wherein a gate is formed on an upper portion of a silicon layer. Referring to FIG. 1, the fabrication method of the conventional top gate type polycrystalline-silicon TFT will now be described.
First, on a semiconductor substrate 11 there is formed a first oxide film 12 serving as an insulation layer. A polysilicon layer 13 is formed on the first oxide film 12 using a chemical vapor deposition ("CVD") method. On the polysilicon layer 13 there is formed a second oxide film 14 serving as another insulation layer. Using a mask (not shown), the second oxide film 14 is selectively etched so as to expose portions of the polysilicon layer 13, which will become the upper surface of source/drain regions. A gate electrode 15 is formed on a portion of the second oxide film 14. Impurities of boron or phosphorous are ion-implanted into the exposed surface of the polysilicon layer 13 so as to form the source and drain regions 16, 17. On the source and drain regions 16, 17, there are respectively formed source and drain electrodes 18, 19, which are electrically connected to a corresponding one of the source and drain regions 16, 17. This completes the fabrication method of the conventional TFT.
In the conventional TFT as shown in FIG. 1, when a voltage higher than the voltage of the source electrode 18 is applied to the drain electrode 19 and a voltage higher than the threshold voltage is applied to the gate electrode 15, electrons flow from the source region 16 to the drain region 17 through a channel region 20 and a driving current also flows accordingly.
In the conventional TFT, however, when a voltage is applied to the gate electrode 15 to form a channel, the carrier movability is decreased due to a potential barrier formed at grain boundaries in an interior of the polysilicon layer 13. Therefore, the driving current significantly decreases due to the potential barrier during a turn-on operation of the TFT and further, owing to such a disadvantage, there occurs an irregular current leakage which may decrease the on/off ratio of the drain current.
By providing an offset region and decreasing the irregular leakage current, the on/off current ratio of the TFT may be increased as disclosed in IEEE Electron Device Letters, Vol. 9, No. 1, January 1988, entitled "Characteristics of Offset Structure Polycrystalline Silicon". A description related to such a TFT will be given below with reference to FIG. 2.
As shown in FIG. 2, on a semiconductor substrate 21 there is formed a polysilicon layer 22 using an LPCVD (Lower Pressure Chemical Vapor Deposition). A low density of phosphorous ions are implanted into defined offset regions 23a, 23b. Then a heat treatment is performed on the substrate 21 at a temperature of 900.degree. C. so as to activate the implanted impurities and define source and drain regions 24a, 24b. On the polysilicon layer 22, a gate insulation layer 25 formed by depositing a material such as SiN thereon. The insulation layer 25 is patterned to define a plurality of contact holes 25' through the gate insulation layer 25. Then an aluminum layer is formed on the gate insulation layer 25 including the contact holes 25'. The aluminum layer is selectively etched so as to form a gate electrode 26, a source electrode 27 and a drain electrode 28. The offset length Ls of the offset regions 23a, 23b varies from 3 .mu.m to 7 .mu.m.
Meanwhile, in accordance with the offset regions 23a, 23b, the TFT in FIG. 2 has a higher on/off current ratio than the conventional TFT in FIG. 1. However, the TFT in FIG. 2 suffers from the disadvantage of decreased current during the "on" period of the TFT because the offset region 23a is in direct contact with and adjacent to the source region 24a.
To correct this problem, a transistor without any offset regions located adjacent the source region has been proposed. However, such a transistor suffers from a problem in that a mask must be provided to define the source/drain regions and the offset regions. Since self-alignment is not achieved in such a transistor, its fabrication process becomes complicated. Further, the offset regions are formed by an ion-implantation and therefore an accurate length of the offset regions may be difficult to obtain.